The present invention relates to data processing systems and, more particularly, to a circuit in such systems for trimming a digital pulse signal.
The circuits in a computer system require the use of many timing, clocking and other digital pulse signals. In a typical system, a portion of the hardware is devoted exclusively to the generation of such signals. Typically, a few basic pulse signals are generated, and the other signals needed by the system are provided by adjusting or processing those basic signals. One pulse signal often needed has the rising edges of its pulses only slightly delayed from the pulses in the basic signal from which it is obtained. A pulse signal which has its rising edges delayed from, but its falling edges coincident with, the corresponding edges of a more basic pulse signal is referred to as a "trimmed" signal.
Circuits for trimming digital pulse signals are known in the art. For example, in U.S. Pat. No. 3,073,971, issued to E. J. Daigle, Jr. on January 15, 1963, there is shown a circuit having an RC integrator and NPN and PNP transistors, including two NPN transistors that form a differential amplifier. The differential amplifier causes the rising edge of an input pulse to be delayed according to the time constant of the RC integrator, but passes the falling edge without delay.
The problem with circuits such as the one disclosed in the Daigle patent is that they are not suited for modern computer circuitry. For example, in a computer having integrated circuit chips fabricated using MOS technology, it would be difficult to include an RC circuit for controlling the signal delay as done in the Daigle patent and, even if done, it would not control the delay with the precision needed for the extremely fast operation of today's integrated circuits. This is readily apparent from a reading of the Daigle patent, which refers to a delay in the rising edge of "10 milliseconds", and then considering the need, in a typical modern computer, for a delay of perhaps 10 nanoseconds.